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1 ? fn6413.0 ISL8723, isl8724 power sequencing controllers the intersil ISL8723 and isl8724 are 4 channel sequencers controlling the on and off sequence of voltages with under voltage supply fault protection and a ?sequence completed? signal (reset#). for larger systems, more than 4 voltages can be sequenced by a simple connection of multiple ic's. these sequencers use an integrat ed charge pump to drive 4 external low-cost n-channel mosfet switch gates above the ic bias voltage by 5.3v. these ic's can be biased from and control any supply from 2.5v to 5v and additionally monitor any voltage above 0.7v. individual product descriptions are below. the four channel ISL8723 (enable input), isl8724 (enable# input) offer the designer 4 voltage control when it is required that all four rails are in minimal compliance prior to turn on and that compliance must be maintained during operation. the ISL8723 has a low power standby mode when it is disabled suitable for battery powered applications. external resistors provide flexible voltage threshold programming of monitored voltages. delay and sequencing timing are programmable by external capacitors for both ramp up and ramp down. features ? enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7v to 5v) ? operates from 2.5v to 5v supply voltage ? supplies v dd +5.3v of charge pumped gate drive ? adjustable voltage slew rate for each rail ? multiple sequencers can be easily daisy-chained to sequence an infinite number of independent voltages ? glitch immunity ? under voltage lockout for each monitored supply voltage ? 30a sleep state ( ISL8723 ) ? active high ( ISL8723 ) or low ( isl8724 ) enable# input ? pb-free plus anneal available (rohs compliant) qfn package applications ? graphics cards ? fpga/asic/microprocessor/powerpc supply sequencing ? network routers ? telecommunications systems pinout ISL8723, isl8724 (24 ld qfn) top view ordering information part number part marking temp. range (c) package pkg. dwg. # ISL8723irz (note) 8723irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4 isl8724irz (note) 8724irz l24.4x4 ISL8723irz-t (note) 8723irz -40 to +85 24 ld 4x4 qfn (pb-free) tape & reel l24.4x4 isl8724irz-t (note) 8724irz l24.4x4 ISL8723eval1 evaluation platform note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 4mmx4mm enable/ enable# gate_a dly_off_c dly_off_d gate_b gate_c gate_d dly_on_b nc gnd nc uvlo_b dly_off_b uvlo_d dly_on_d dly_on_c uvlo_c dly_off_a nc uvlo_a dly_on_a sysrst# vdd reset# data sheet december 21, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners.
2 fn6413.0 december 21, 2006 figure 1. typical ISL8723 application usage aout ain bin cin din bout cout dout uvlo_b uvlo_a uvlo_d uvlo_c ain dly_on_a dly_off_a dly_off_b dly_off_c dly_off_d dly_on_b dly_on_c dly_on_d enable sysrst# ground bin cin din reset# vdd gate d gate c gate b gate a pin descriptions pin # pin name function description 23 vdd chip bias bias ic from nominal 2.5v to 5v 10 gnd bias return ic ground 1 enable/ enable# input to start on/off sequencing. input to initiate the start of the programmed sequenc ing of supplies on or off. enable functionality is disabled for 10ms after uvlo is satisf ied. ISL8723 has enable. isl8724 has enable#. 24 reset# reset# output reset# provides a high signal ~160ms after all gates are fully enhanced. this delay is for stab ilization of output voltages. reset# will assert low upon any uvlo not being satisfied or enable/enable# being deasserted. the reset# output is an open drain n-channel fet and is guaranteed to be in the correct state for vdd down to 1v and is filtered to ignore fast transients on vdd and uvlo_x. 20 uvlo_a under voltage lock out/monitoring input these inputs provide for a programmable uv lockout referenced to an internal 0.631v reference and are filtered to ignore short (<7s) transients below programmed uvlo level. 12 uvlo_b 17 uvlo_c 14 uvlo_d 21 dly_on_a gate on delay timer output allows for programming the delay and sequence for v out turn-on using a capacitor to ground. each cap is charged with 1a, 10ms after turn-on initia ted by enable/enable# with an internal current source providing delayed enhancement of t he associated fets gate to turn-on. 8dly_on_b 16 dly_on_c 15 dly_on_d 18 dly_off_a gate off delay timer output allows for programming the delay and sequence for v out turn-off through enable/enable# via a capacitor to ground. each cap is charged with a 1a internal current source to an internal reference voltage causing the corresponding gate to be pulled down thus turning-off the fet. 13 dly_off_b 3 dly_off_c 4 dly_off_d 2 gate_a fet gate drive output drives the external fets with a 10a current source to soft start ramp into the load. during sequence off, 10a is sunk from this pin to control the fet turn-off. during a turn-off due to a fault, the gate will sink ~75ma to ensure a rapid turn-off. 5gate_b 6gate_c 7gate_d ISL8723, isl8724
3 fn6413.0 december 21, 2006 22 sysrst# system reset i/o as an input, allows for immediate and unconditional latch-off of all gate outputs when driven low. thi s pin can also be used to initiate the programmed sequence with ?zero? wait (no 10ms stabilization delay) from input signal on this pin being driven high to first gate. as an output when there is a uv condition this pin pulls low. if common to other sysrst# pins in a multiple ic configuration it will ca use immediate and unconditional latch-off of all other gates on all other isl872x sequencers. this pin is released to go high once all uvlo and enable conditions are satisfied and is pulled low concurrent with the last gate being turned off after en disabled. 9,11, 19 no connect no connect no connect pin descriptions (continued) pin # pin name function description ISL8723, isl8724
4 fn6413.0 december 21, 2006 absolute maximum rati ngs thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0v gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +6v uvlo, enable, enable#, sysrst# . . . . . . -0.3v to v dd +0.3v reset#, dly_on, dlyoff . . . . . . . . . . . . . . . -0.3v to v dd +0.3v operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . . . +2.5v to +5.0v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 4 x 4 qfn package . . . . . . . . . . . . . . . 48 9 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . +125c maximum storage temperature range . . . . . . . . . .-65c to +150c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 3. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 3.3v to +5v, t a = t j = -40c to +85c, unless otherwise specified. parameter symbol test conditions min typ max unit uvlo undervoltage lockout falling threshold v uvlovth t a = t j = +25c 619 631 647 mv undervoltage lockout falling threshold v uvlovth 604 631 656 mv undervoltage lockout hysteresis v uvlohys -9-mv undervoltage lockout threshold range ruvlovth max v uvlovth - min v uvlovth -618mv undervoltage lockout delay tuvlodel enable satisfied - 10 - ms transient filter duration tfil v dd , uvlo, enable glitch filter - 7 - s delay on/off delay charging current dly_ichg v dly = 0v 0.9 1 1.115 a delay charging current range dly_ichg_r dly_ichg(max) - dly_ichg(min) - 0.01 0.05 a delay threshold voltage dly_vth 1.21 1.273 1.32 v enable/enable#, reset# and sysrst# i/o enable threshold v enh measured at v dd = 5v - 1.28 1.35 v enable# threshold v enh -0.5 v dd -v enable/enable# hysteresis v enh - v enl measured at v dd = 5v - 0.1 0.2 v enable/enable# lockout delay tdelen_lo uvlo satisfied, en to dly_on - 10 - ms enable/enable# input capacitance cin_en - 5 - pf reset# pull-up voltage vpu_rst - v dd -v reset# pull-down current i rst pd5 v dd = 5v, rst = 0.1v - 13 - ma reset# delay after gate high t rst del gate = v dd +5v - 160 - ms reset# output low v rst l measured at v dd = 5v, 1ma sourcing current --0.1v reset output capacitance cout_rst - 10 - pf sysrst# pull-up voltage vpu_srst - v dd -0.5v - v sysrst# pull-up current ipu_srst v dd = 3.3v, sysrst# = 0.5v - 12 - a sysrst# pull down current ipu_5 v dd = 5v - 2.7 - a sysrst# low output voltage vol_srst v dd = 5v, i out = 100 a- 0.1v ISL8723, isl8724
5 fn6413.0 december 21, 2006 ISL8723, isl8724 descriptions and operation the ISL8723 and isl8724 sequencers are quad voltage sequencing controllers designed for use in multiple-voltage systems requiring power s equencing of various supply voltages. individual voltage rails are gated on and off by external n-channel mosfets, the gates of which are driven by an internal charge pump to ~v dd +5.6v (vqp) in a user programmed sequence. with the ISL8723 the enable must be asserted high and all four voltages to be sequenced must be above their respective user programmed under voltage lock out (uvlo) levels before pr ogrammed output turn on sequencing can begin. sequencing and delay determination is accomplished by the choice of external cap values on the dly_on and dly_off pins. the sysrst# goes high once all 4 uvlo inputs and enable are satisfied. once all 4 uvlo inputs and enable are satisfied for 10ms, the four dly_on caps are simultaneously charged with 1 a current sources to the dly_vth level of 1.28v. as each dly_on pin reaches the dly_vth level its associated gate will then turn-on with a 10 a source current to the vqp voltage of vdd+5.6v. thus all four gates will sequentially turn on. once at dly_vth the dly_on pins will discharge to be ready when next needed. after the entire turn on sequence has been completed and all gates have reached the charge pumped voltage (vqp), a 160ms delay is started to ensure stability after which the reset# output will be released to go high. subsequent to turn-on, if any input falls below its uvlo point for longer than the glitch filter period, t fil (~7 s) this is considered a fault. reset#, sysrst# and all gates are simultaneously pulled low. in this mode the gates are pulled low with ~75ma. normal shutdown mode is entered when no uvlo is violated and the enable is deasserted. when enable is deasserted, reset# is asserted and pulled low. next, all four shutdown ramp caps on the dly_off pins are charged with a 1 a source and when any ramp-cap reaches dly_vth, a latch is set and a 10 a current is sunk on the respective gate pin to turn off its external mosfet. when the falling gate voltage is approximately 1.5v, the gate is pulled down the rest of the way at a higher current level to ensure a hard turn-off. each individual external fet is thus turned off removing the voltages from the load in th e programmed sequence. the sysrst# will pull low concurrent with the last gate being pulled low. the ISL8723 and isl8724 have the same functionality except for the complimentary enable active polarity with the isl8724 having an enable# input. additionally the ISL8723 also has a low power sleep state when disabled. upon bias the sysrst# and reset# pins are held low before bias voltage = 1v. the sysrst# has both an input and output function. as an output the sysrst# pin is useful when implementing multiple sequencers in a design needing simultaneous shutdown as with a kill switch across all sequencers. once any uvlo is unsatisfi ed for longer than t fil the related sysrst# will pull low and pull all other sysrst# pins low that are on a common connection thus unconditionally shutting down all outputs across multiple sequencers. as an input, if it is pulled low all gates will be unconditionally shut off and reset# pulled low, see figure 17. this pin can also be used as a ?no wait? enabling input, if all inputs (enable and uvlo) are satisfied it does not wait through sysrst# output capacitance cout_srst - 10 - pf sysrst# low to gate turn-off t delsys_g_1 gate = 80% of v dd +5v - 40 - ns sysrst# high to gate turn-on t delsys_g_2 gate = 50% of v dd +5v - 0.4 - ms gate gate turn-on current i gateon gate = 0v 8.3 10.2 12.5 a gate turn-off current i gateoff_l gate = v dd , disabled -12.5 -10.2 -8.3 a gate current range i gate_range within ic i gate max-min - 0.6 3 a gate pull-down high current i gateoff_h gate = v dd , uvlo = 0v - 75 - ma gate high voltage v gateh5 v dd = 5v v dd +5.3v v dd +5.6v - v gate low voltage v gatel gate low voltage, v dd = 1v - 0.01 0.1 v bias ic supply current i vdd_5v v dd = 5v, enabled and static - 0.27 0.31 ma ISL8723 stand by ic supply current i vdd_sb v dd = 5v, enable = 0v - 30 40 a v dd power on reset v dd _por v dd rising - 2.2 2.41 v electrical specifications v dd = 3.3v to +5v, t a = t j = -40c to +85c, unless otherwise specified. (continued) parameter symbol test conditions min typ max unit ISL8723, isl8724
6 fn6413.0 december 21, 2006 the ~10ms enable delay to initiate dly_on cap charging when released to go high. this feature can be used where 4 voltages can be monitored in addition to a on-off switch position or, in the case of the isl8724 a present pin pull down. restart of the turn on sequence is automatic once all requirements are met. this allows for no interaction between the sequencer and a controller ic if so desired. if no capacitors are connected between dly_on or dly_off pins and ground then all such related gates start to turn on immediately after the 10ms (t uvlodel ) enable stabilization time out has expired and the gates start to immediately turn off when enable is deasserted. table 1 illustrates the nominal time delay from the start of charging to the 1.27v reference for various capacitor values on the dly_x pins. this table does not include the 10ms of enable lock out delay during a start up sequence but represents the time from the end of the enable lock out delay to the start of gate transition. there is no enable lock out delay for a sequence off, so this table illustrates the delay to gate transition from a disable signal. figure 2 illustrates the turn-on and figure 3 the nominal turnoff timing diagrams of the ISL8723 and isl8724 product. note the delay and flexible sequencing possibilities. multiple series, parallel or adjustable capacitors can be used to easily fine tune timing between that offered by standard value capacitors. table 1. nominal delay to sequencing threshold dly pin capacitance time (ms) open 0.02 100pf 0.135 1000pf 1.35 0.01 f13.5 0.1 f 135 1 f 1350 note: nom. t del_seq = dly_cap (f) x 1.35m ISL8723, isl8724
7 fn6413.0 december 21, 2006 l figure 2. ISL8723, isl8724 turn-on a nd glitch response timing diagram uvlo_b uvlo_c uvlo_d enable (ISL8723) reset# dlyon_a dlyon_b dlyon_c dlyon_d gate_a gate_b gate_c gate_d uvlo_a v en dly_vth dly_vth dly_vth dly_vth v qpump v qpump v qpump enable# (isl8724) v uvlovth v uvlovth v uvlovth v uvlovth t rstdel t uvlodel v qpump -1v v qpump ISL8723, isl8724 turn-off timing diagram enable# (isl8724) reset# dlyoff_a dlyoff_b dlyoff_c dlyoff_d gate_d gate_c gate_b gate_a enable(ISL8723) v en uvlo_x>vuvlovth dly_vth dly_vth dly_vth dly_vth sysrst# ISL8723, isl8724
8 fn6413.0 december 21, 2006 typical performance curves figure 4. bias current figure 5. uvlo threshold voltage figure 6. dly threshold voltage figure 7. dly charge current figure 8. bias power on reset figure 9. charge pump voltage 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -40-20 0 25457585100125 temperature (c) bias current (ma) v dd = 5v v dd = 3.3v ISL8723 disabled 610 615 620 625 630 635 640 645 650 -40 -20 0 25 45 75 85 100 125 temperature (c) uvlo (mv) 1.23 1.24 1.25 1.26 1.27 1.28 1.29 -40 -20 0 25 45 75 85 100 125 temperature (c) dly vth (v) dly_on vth dly_off vth 0.920 0.940 0.960 0.980 1.000 1.020 -40 -20 0 25 45 75 85 100 125 temperature (c) dly_on/off current (a) dly_on dly_off 1.23 1.24 1.25 1.26 1.27 1.28 1.29 -40 -20 0 25 45 75 85 100 125 temperature (c) dly vth (v) dly_on vth dly_off vth 4.8 5.0 5.2 5.4 5.6 5.8 6.0 -40 -20 0 25 45 75 85 100 125 temperature (c) q-pump voltage (v) v dd = 5v v dd = 2.5v ISL8723, isl8724
9 fn6413.0 december 21, 2006 using the ISL8723eval1 platform the ISL8723eval1 platform allows evaluation of the ISL8723, easily providing access to the critical nodes, see figure 21 for schematic and figure 22 for a photograph of the evaluation platform. the board has a smd layout with a ISL8723 illustrating the possible small implementation size for a typical four rail sequencing application. there are bias and function labeled test points to give access to the ic pins for evaluation. remember that significant current or capacitive loading of particular i/o pins will affect functionality and performance. the default config uration of the ISL8723eval1 circuit was built around the following design assumptions: 1. using the ISL8723ir 2. the four supplies being sequenced are 5v (in_a), 3.3v (in_b), 2.5v (in_d) and 1.5v (in_c), the uvlo levels are ~80% of nominal voltages. resistors chosen such that the total resistance of each divider is ~ 10k using standard value resistors to approximate 80% of nominal voltage supply = 0.63v on uvlo input. 3. the desired order turn-on sequence is 5v first, then 3.3v about 12ms later then the 2. 5v supply about 19ms later and lastly the 1.5v supply about 40ms later. 4. the desired turn-off sequence is first the 2.5v, the 3.3v 12ms later, then the 1.5v supply about 36ms later and lastly the 5v supply about 72ms after that. 5. led off indicates sequence has completed and reset has released and pulled high. all scope shots are taken from ISL8723eval1 board. figures 12 and 13 illustrate the desired turn-on and turn-off sequences respectively. the sequencing order and delay between voltages sequencing is set by external capacitance values so other than that illustrated can be accomplished. figures 14 and 15 illustrate the timing relationships between the en input, reset#, dly and gate outputs and the vout voltage for a single channel being turned on and off respectively. reset# and sysrst# functiona lity and relationships are shown in figures 16 through 20. figure 16 illustrates that with a rising vdd, en tied to vdd, and all uvlo co nfigured to be satisf ied, both the reset# and sysrst# are held low before vdd = 1v. sysrst# is released to go high once the last uvlo is satisfied and reset# is released to go high at t rst del after the last gate is high. figure 17 shows gate and reset# response to sysrst# being pulled low. figure 18 shows en high to sysrst# delay with all uvlo inputs satisfied. figure 19 shows reset# and sysrst# delay to en pulled low. figure 20 shows ~8s of glitch filter duration, tfil during which the reset# and sysrst# do not react. figure 10. gate turn-off/on (dis)charge current figure 11. fault gate turn-off sink current typical performance curves (continued) 9.4 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 -40 -20 0 25 45 75 85 100 125 temperature (c) gate current (a) i_gate_off i_gate_on 40 50 60 70 80 90 100 -40-20 0 25457585100125 temperature (c) fault gate current (ma) ISL8723, isl8724
10 fn6413.0 december 21, 2006 ISL8723, isl8724 typical performance waveforms figure 12. ISL8723 sequenced turn-on figure 13. ISL8723 sequenced turn-off figure 14. ISL8723 3.3v turn-on fi gure 15. ISL8723 3.3v turn-off figure 16. sysrst# and reset# vs vdd (en = vdd, 4 uvlo > uvlo vth) figure 17. sysrst# low to gate and reset# low vout = 2v/div 40ms/div 5vout 3.3vout 2.5vout enable 1.5vout i/o = 5v/div reset# sysrst# vout = 2v/div 20ms/div reset# 3.3vout 2.5vout 1.5vout sysrst# enable 5vout i/o = 5v/div 4ms/div gate 2v/div dly_vth en 5v/div dly_on 0.5v/div 3.3vo 2v/div t delenlo 10ms/div 3.3vo 2v/div gate 2v/div en 5v/div dly_off 0.5v/div dly_vth reset# vdd sysrst# sysrst# reset# gate
11 fn6413.0 december 21, 2006 figure 18. 4 uvlos valid, enable hi gh to sysrst high figure 19. e nable low to reset# and sysrst low figure 20. uvlo invalid to reset# and sysrst$# low typical performance waveforms (continued) enable sysrst# enable sysrst# reset# sysrst# reset# uvlo ISL8723, isl8724
12 fn6413.0 december 21, 2006 +2.5v 1.5v +3.3v +5v c1 1 f c2 0.01 f 0.022 f open 0.068 f c3 c5 c4 c6 0.047 f c8 0.01 f c7 open c9 0.1 f nc sysrst gnd reset gate_c gate_d gate_b gate_a ISL8723ir uvlo_a dly_off_b uvlo_d uvlo_c uvlo_b dly_off_d dly_off_c dly_on_a u1 dly_on_c dly_on_d dly_on_b v dd enable 3.01k 1.47k 4.99k r12 r3 en r1 r4 r2 r6 7.681k 4.99k 6.98k 8.45k 12 17 14 20 22 9,11 r9 750 2 5 7 6 sysrst 3 4 13 18 21 16 15 8 23 q1a 4 5 3 2 q1b 7 5 6 r9 10 r10 10 r13 10 r14 10 2 4 3 fds6990s fds6990s fds6990s 8 6 fds6990s 1 8 q2b dly_off_a r5 r11 10 1 1 24 2.26k figure 21. ISL8723eval1 board schematic 7 1 q2a 19 d1 figure 22. eval board photograph ISL8723, isl8724
13 fn6413.0 december 21, 2006 table 2. isl872xseqeval1 board component listing component designator component function component description u1 ISL8723 , 4 supply sequencer intersil, ISL8723ir 4 supply sequencer q1, q2 voltage rail switches fds6990s or equiv, dual n-channel mosfet r6 5v to uvlo_a resistor for divider string 8.45k 1%, 0402 r11 uvlo_a to gnd resistor for divider string 1.47k 1%, 0402 r1 3.3v to uvlo_b resistor for divider string 7.68k 1%, 0402 r12 uvlo_b to gnd resistor for divider string 2.26k 1%, 0402 r2 2.5v to uvlo_d resistor for divider string 6.98k 1%, 0402 r3 uvlo_d to gnd resistor for divider string 3.01k 1%, 0402 r4 1.5v to uvlo_c resistor for divider string 4.99k 1%, 0402 r5 uvlo_d to gnd resistor for divider string 4.99k 1%, 0402 r9 reset led current limiting resistor 750 10%, 0805 c5 5v turn-on delay cap. a (~10ms) dnp, 0402 c9 5v turn-off delay cap. a (~140ms) 0.1 f 10%, 6.3v, 0402 c2 3.3v turn-on delay cap.b (~13ms) 0.01 f 10%, 6.3v, 0402 c8 3.3v turn-off delay cap. b (~13ms) 0.01 f 10%, 6.3v, 0402 c3 2.5v turn-on delay cap.d (~25ms) 0.022 f 10%, 6.3v, 0402 c7 2.5v turn-off delay cap. d (0ms) dnp, 0402 c4 1.5v turn-on delay cap. c (~100ms) 0.068 f 10%, 6.3v, 0402 c6 1.5v turn-off delay cap. c (~60ms) 0.047 f 10%, 6.3v, 0402 c1 decoupling capacitor 1 f, 0805 d1 reset indicating led 0805, smd leds red r9 5v load resistor 10 20%, 3w carbon r10 3.3v load resistor 10 20%, 3w carbon r13 2.5v load resistor 10 20%, 3w carbon r14 1.5v load resistor 10 20%, 3w carbon test points labeled as to function ISL8723, isl8724
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6413.0 december 21, 2006 application implementations multiple sequencer implementations in order to control the sequencing of more than 4 voltages in applications where the integrity of these critical voltages must be assured prior to sequencing, several of the ISL8723 or isl8724 devices can configured together to accomplish this. figure 23 shows a typical multi sequencer implementation, note the common sysrst# signal that asserts once all monitored voltages are valid allowing the sequence to initiate. the sequencing is straight forward across multiple sequencers as all dly_on capacitors will simultaneously start charging once all monitored voltages area valid and ~10ms after the common enable input signal is delivered. this allows the choice of capa citors to be related to each other no different than using a single sequencer. when the common enabling signal is deasserted this configuration will then execute the turn-off sequence across all sequencers as programmed by the dly_off capacitor values. with all the sysrst# pins bused together once the on sequence is complete simultaneous shutdown upon any uvlo input failure is assu red as the sysrst# output will pull low, simultaneously turning off all gate outputs. figure 23. multiple isl872x configuration isl872x enable# uvlo g a t e power supply sysrst# reset# high = power good enable isl872x enable# uvlo g a t e sysrst# reset# high = sequence completed ISL8723, isl8724
15 fn6413.0 december 21, 2006 ISL8723, isl8724 package outline drawing l24.4x4 24 lead quad flat no-lead plastic package rev 4, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 10 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 10 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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